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portada Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc
Design of Cost-Efficient Interconnect Processing Units: Spidergon StnocDesign of Cost-Efficient Interconnect Processing Units: Spidergon StnocDesign of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc
Type
Physical Book
Author
Publisher
Language
English
Pages
288
Format
Hardcover
Dimensions
23.6x16.3x2.5 cm
Weight
0.66 kg.
ISBN
1420044710
ISBN13
9781420044713
Categories

Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc

Marcello Coppola (Author) · Miltos D. Grammatikakis (Author) · Riccardo Locatelli (Author) · CRC Press · Hardcover

Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc - Coppola, Marcello ; Grammatikakis, Miltos D. ; Locatelli, Riccardo

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Synopsis "Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc"

Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.A Balanced Analysis of NoC ArchitectureAs the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.

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