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portada Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling
Type
Physical Book
Publisher
Language
English
Pages
143
Format
Paperback
Dimensions
23.4x15.6x0.9 cm
Weight
0.23 kg.
ISBN13
9781493948178

Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Ayan Mandal (Author) · Sunil P. Khatri (Author) · Rabi Mahapatra (Author) · Springer · Paperback

Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling - Mandal, Ayan ; Khatri, Sunil P. ; Mahapatra, Rabi

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Synopsis "Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling"

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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