Name: Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis
SKU: 54537451
Price: 61.75 EUR
Availability: InStock
Author: Goossens, Bernard
ISBN: 9783031180224

portada Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis

Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis

Type

Physical Book

Author

Bernard Goossens

Publisher

Springer

Language

English

Pages

439

Format

Paperback

Dimensions

22.8x14.8x1.6 cm

Weight

0.77 kg.

ISBN13

9783031180224

Synopsis "Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis"

This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore).Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors).The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development.Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators.Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.

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Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis - Goossens, Bernard

Synopsis "Guide to Computer Processor Architecture: A Risc-V Approach, with High-Level Synthesis"

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