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portada Network -On-Chip (NOC) Design Using FPGA Technology
Type
Physical Book
Author
Publisher
Language
English
Pages
76
Format
Paperback
Dimensions
22.9x15.2x0.5 cm
Weight
0.12 kg.
ISBN13
9786138919360
Categories

Network -On-Chip (NOC) Design Using FPGA Technology

Manish Jain (Author) · Scholars' Press · Paperback

Network -On-Chip (NOC) Design Using FPGA Technology - Jain, Manish

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Synopsis "Network -On-Chip (NOC) Design Using FPGA Technology"

NoC is new paradigm for System-on-chip (SoC) design. NoC based system accommodate multiple asynchronous clocking that many of today's complex SoC design use.The NoC solutions bring a Networking method on-chip communication and claim roughly a performance increases over conventional bus system. As a systematic approach, Network-on-Chip (NoC) called also Network-on-Silicon, proposes networks as a scalable, reusable and global communication architecture to overcome the pains of future System-on-Chip.The idea of NoC is derived from large-scale computer networks and distributed computing. However, the routing techniques for NoC have some unique design considerations besides low latency and high throughput. Due to tight constraints on memory and computing resources, the routing techniques for NoC should be reasonably simple. Several switch architectures have been developed for NoC employing XY output selection and wormhole routing.NoC is a layered approach for on-chip communication design proposed in literature to cope with issues of current SoC architectures. A scalable communication infrastructure that better supports the trend of SoC integration consists of an on-chip packet-swit.

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